;------------------------------------------------------------------------------ ; Title : bsa.asm ; Description : Brick Spine for AVR ; The original is a "Brick Spine 2" which Mr. Hirota developed. ; Author : KAWAMOTO "nanashino" Yasuhisa ; Email : nanashi@yk.rim.or.jp ; Date : 09/22/2000 ;------------------------------------------------------------------------------ ;------------------------------------------------------------------------------ ; History : 09/22/2000 TOV0フラグのクリア忘れ修正 ; 09/04/2000 初期バージョン ;------------------------------------------------------------------------------ .include "2313def.inc" ;-- Defined constant -- .equ N0 = 125 ; 250us@4.0MHz and R0=2 .equ R0 = 2 ; 1/8 .equ N1 = 10000 ; 2.5ms@4.0MHz and R1=1 .equ PWMP1 = 1000 ; 0.25ms@4.0MHz and R1=1 .equ PWMW1 = 533 ; 133us@4.0MHz and R1=1 .equ R1 = 1 ; 1/1 ;-- Global register -- .def t_tmp = r16 ; Scratch register(in interrupt handler) .def t_tmp2 = r17 ; Scratch register2(in interrupt handler) .def t_tmp3 = r18 ; Scratch register3(in interrupt handler) .def t_sr = r19 ; SREG storage(in interrupt handler) .def t_reld0 = r20 ; Reload register0(in tim0_ovf) .def rcx_wc = r1 ; RCX width counter .def rcx_c0 = r2 ; RCX counter0 .def rcx_c1 = r3 ; RCX counter1 .def rcx_c2 = r4 ; RCX counter2 .def rcx_c3 = r5 ; RCX counter3 .def rcx_bf0 = r6 ; RCX buffer0 .def rcx_bf1 = r7 ; RCX buffer1 .def rcx_st = r21 ; RCX status .def t_reld1h = r22 ; Reload high register1(in tim1_ovf) .def t_reld1l = r23 ; Reload low register1(in tim1_ovf) .def pwm_oc = r24 ; PWM output channel .def tmp = r25 ; Scratch register .def tmp2 = r26 ; Scratch register2 ; r28-r29 is Y-Register ; r30-r31 is Z-Register ;-- Bit position in Status register -- .equ RCBF = 7 ; RCX command buffer full .dseg .org $60 ;-- Servo PWM paramter -- pwm_in: .byte 8 pwm_out: .byte 8 pwm_r1: .byte 8 pwm_r2: .byte 8 .cseg ;-- Reset and interrupt vector -- .org $0000 rjmp main ; Reset Handler .org INT0addr reti ; IRQ0 Handler(Not Used) .org INT1addr reti ; IRQ1 Handler(Not Used) .org ICP1addr reti ; Timer1 Capture Handler(Not Used) .org OC1addr rjmp tim_comp1 ; Timer1 Compare Handler .org OVF1addr rjmp tim1_ovf ; Timer1 Overflow Handler .org OVF0addr rjmp tim0_ovf ; Timer0 Overflow Handler .org URXCaddr reti ; UART RX Complete Handler(Not Used) .org UDREaddr reti ; UDR Empty Handler(Not Used) .org UTXCaddr reti ; UART TX Complete Handler(Not Used) .org ACIaddr reti ; Analog Comparator Handler(Not Used) ;-- RCX signal receive(in tim0_ovf) -- rcx: sbis PIND,0 ; RCX-A FWD inc rcx_c0 sbis PIND,1 ; RCX-A RVS inc rcx_c1 sbis PIND,2 ; RCX-B FWD inc rcx_c2 sbis PIND,3 ; RCX-B RVS inc rcx_c3 dec rcx_wc brne rcx_exit sbrc rcx_st,RCBF ; Check clear RCBF rjmp rcx_skip inc rcx_c0 ; rcx_c0 = (rcx_c0+2)/4 inc rcx_c0 lsr rcx_c0 lsr rcx_c0 inc rcx_c1 ; rcx_c1 = (rcx_c1+2)/4 inc rcx_c1 lsr rcx_c1 lsr rcx_c1 inc rcx_c2 ; rcx_c2 = (rcx_c2+2)/4 inc rcx_c2 lsr rcx_c2 lsr rcx_c2 inc rcx_c3 ; rcx_c3 = (rcx_c3+2)/4 inc rcx_c3 lsr rcx_c3 lsr rcx_c3 tst rcx_c0 ; if rcx_c0 != 0 goto rcx_00 brne rcx_00 tst rcx_c1 ; if rcx_c1 == 0 goto rcx_00 breq rcx_00 ldi t_tmp,8 ; rcx_c0 = rcx_c1+8 add rcx_c1,t_tmp mov rcx_c0,rcx_c1 rcx_00: tst rcx_c2 ; if rcx_c2 != 0 goto rcx_01 brne rcx_01 tst rcx_c3 ; if rcx_c3 == 0 goto rcx_01 breq rcx_01 ldi t_tmp,8 ; rcx_c2 = rcx_c3+8 add rcx_c3,t_tmp mov rcx_c2,rcx_c3 rcx_01: cp rcx_bf0,rcx_c0 ; if rcx_bf0 == rcx_c0 goto rcx_02 breq rcx_02 mov rcx_bf0,rcx_c0 rjmp rcx_skip rcx_02: cp rcx_bf1,rcx_c2 ; if rcx_bf1 == rcx_c2 goto rcx_03 breq rcx_03 mov rcx_bf1,rcx_c2 rjmp rcx_skip rcx_03: tst rcx_bf0 ; if rcx_bf0 == 0 goto rcx_skip breq rcx_skip tst rcx_bf1 ; if rcx_bf1 == 0 goto rcx_skip breq rcx_skip sbr rcx_st,(1<