;------------------------------------------------------------------------------ ; Title : wc.asm ; Description : WonderCommand ; Author : KAWAMOTO "nanashino" Yasuhisa ; Email : nanashi@yk.rim.or.jp ; Date : 07/28/2000 ;------------------------------------------------------------------------------ .include "1200def.inc" ;-- Modulation-freq(38.4KHz) setting -- .equ N=52 ; 13us@4.0MHz and R=1 ;.equ N=130 ; 13us@10.0MHz and R=1 .equ R=1 ; 1/1 .equ BAUD_9600=8 ; .equ BAUD_2400=32 ; ;-- Global register -- .def t_tmp =r16 ; Scratch register .def t_sr =r17 ; Status register storage .def t_reload =r18 ; Reload register .def t_st =r19 ; Status register .def t_rsv_wc =r20 ; IR receive wait counter .def t_rsv_bc =r21 ; IR receive bit counter .def t_rsv_bf =r22 ; IR receive buffer .def t_trn_wc =r23 ; IR tramsmit wait counter .def t_trn_bit =r24 ; IR tramsmit bit register .def t_trn_wave =r25 ; IR tramsmit modulation wave .def trn_one_c =r26 ; IR tramsmit '1' counter .def trn_bf =r27 ; IR tramsmit buffer .def tmp =r28 ; Scratch register .def tmp2 =r29 ; Scratch register2 ;-- Bit position in Status register -- .equ RD =0 ; IR receive data ready bit .equ TR =7 ; IR tramsmit ready bit .cseg ;-- Reset and interrupt vector -- .org $0000 rjmp main ; Reset handler .org INT0addr reti ; External interrupt handler (Not Used) .org OVF0addr rjmp tim0_ovf ; Timer0 overflow handler .org ACIaddr reti ; Analog comparator handler (Not Used) ;-- Timer0 overflow handler -- tim0_ovf: in t_sr,SREG ; Store SREG out TCNT0,t_reload ; Reload timer ;-- Modulation wave output -- com t_trn_wave mov t_tmp,t_trn_bit or t_tmp,t_trn_wave out PORTB,t_tmp dec t_trn_wc brne trn_skip ldi t_trn_wc,BAUD_2400 sbr t_st,(1<