;------------------------------------------------------------------------------ ; Title : wc2.asm ; Description : WonderCommand-II ; Author : KAWAMOTO "nanashino" Yasuhisa ; Email : nanashi@yk.rim.or.jp ; Date : 12/10/2000 ;------------------------------------------------------------------------------ ;------------------------------------------------------------------------------ ; History : 12/10/2000 Idle Mode対応 ; transmit内でtmpを使用していたのを修正 ; 08/07/2000 初期バージョン ;------------------------------------------------------------------------------ .include "2323def.inc" ;-- Defined constant -- .equ N = 52 ; 13us@4.0MHz and R=1 .equ R = 1 ; 1/1 .equ BAUD_9600 = 8 .equ BAUD_2400 = 32 .equ BUFF_SIZE = 32 ;-- Global register -- .def t_tmp = r16 ; Scratch register(in interrupt handler) .def t_sr = r1 ; SREG storage(in interrupt handler) .def t_reld = r2 ; Reload register(in interrupt handler) .def rsv_wc = r17 ; Serial receive wait counter .def rsv_bc = r18 ; Serial receive bit counter .def rsv_bf = r19 ; Serial receive buffer .def trn_bit = r3 ; IR tramsmit bit register .def trn_wv = r4 ; IR tramsmit modulation wave .def trn_wc = r20 ; IR tramsmit wait counter .def trn_bc = r21 ; IR tramsmit bit counter .def trn_1c = r22 ; IR tramsmit '1' counter .def trn_bf = r23 ; IR tramsmit buffer .def str = r24 ; Status register .def bfc = r25 ; Buffer counter .def tmp = r26 ; Scratch register ; r28-r29 is Y-Register used as write pointer ; r30-r31 is Z-Register used as read pointer ;-- Bit position in Status register -- .equ TDBF = 7 ; IR tramsmit data buffer full .equ RBSY = 0 ; Serial receive busy .dseg .org $60 ;-- Buffer area -- bf_start: .byte BUFF_SIZE bf_end: .cseg ;-- Reset and interrupt vector -- .org $0000 rjmp reset ; Reset handler .org INT0addr rjmp ext_int0 ; External interrupt handler .org OVF0addr rjmp tim_ovf0 ; Timer0 overflow handler ;-- External interrupt handler -- ext_int0: in t_sr,SREG ; Store SREG sbr str,(1<