Hyundai (Hynix) 製 8MByte*8=64MByte SDRAMをNios上で使う ●SDRAM Controllerの設定● *Memory Size SDRAM data width = 32 SDRAM address width : row=12 column=8 Number of independent SDRAM chip selects = 1? 2? 4? 8? *Timing Minimum supported CAS latency = 2 Issue one refresh command every = 15.625 us Delay after powerup, befor initializzation = 100 us (?) Duration of refresh command (t_rfc) = 65 ns Duration of precharge command (t_rp) = 20 ns ACTIVE to READ or WRITE delay (t_rcd) = 20 ns Access time (t_ac) = 6 ns Write recovery time (t_wr) Auto precharge = 2 clocks + 7 ns Non-auto precharge = 14 ns *Advanced Settings Cycles after Load Mode Register command (t_mrd) = 2 Number of refresh commands during initialization = 2 Delay(us) after NOP during initialization = 0 ●概要● ------------------------------------------------------------------------ Nios pinname APEX pinname 144pin SDRAM HY57V64820HG ------------------------------------------------------------------------ ▲クロック▲ clk_apex_out CL[1..0] clock cke cke[1..0] CKE[1..0] clock enable ------------------------------------------------------------------------ ▲チップセレクト▲ sd_cs_n s0_n S0 Chip Select VCC s1_n S1 ------------------------------------------------------------------------ ▲バンクアドレス▲ sd_ba[1..0] ba[1..0] BA[1..0] bank address ------------------------------------------------------------------------ ▲アドレスバス▲ sd_a[11..0] a[13..0] A[13..0] アドレスバス 残りはGNDへ ------------------------------------------------------------------------ ▲データバス▲ sd_dq[31..0] dq[63..0] DQ[63..0] データバス 残りは配線しない（トリステートのハイインピーダンス状態にしておく） ------------------------------------------------------------------------ ▲バッファーコントロール(Read時)＆インプットマスク(Write時)▲ sd_dqm[3..0] dqm[7..0] DQMB[7..0] Data Input/Output Mask 残りはVCCへ ------------------------------------------------------------------------ ▲制御信号▲ sd_ras_n ras_n RAS Row Address Strobe sd_cas_n cas_n CAS Colum Address Strobe sd_we_n we_n WE Write Enable ------------------------------------------------------------------------ ???? dnu NU ???? scl SCL ???? sda SDA ------------------------------------------------------------------------ ●詳細● SDRAM Pin Assignment SDRAM Apex minimal 割り当て Pinout Desig- Pin sdram 32 られるべき No. nation No. Pin Name Pin Name ------------------------------------------------------------------------ 1 Vss GND 2 Vss GND 3 DQ0 V19 sdram_dq[0] sdram_dq[0] 4 DQ32 AB5 sdram_dq[32] 5 DQ1 U20 sdram_dq[1] sdram_dq[1] 6 DQ33 AA5 sdram_dq[33] 7 DQ2 W4 sdram_dq[2] sdram_dq[2] 8 DQ34 AA4 sdram_dq[34] 9 DQ3 V4 sdram_dq[3] sdram_dq[3] 10 DQ35 AB4 sdram_dq[35] 11 Vdd +3.3V 12 Vdd +3.3V 13 DQ4 W3 sdram_dq[4] sdram_dq[4] 14 DQ36 AB3 sdram_dq[36] 15 DQ5 Y3 sdram_dq[5] sdram_dq[5] 16 DQ37 AB19 sdram_dq[37] 17 DQ6 V3 sdram_dq[6] sdram_dq[6] 18 DQ38 AB20 sdram_dq[38] 19 DQ7 Y19 sdram_dq[7] sdram_dq[7] 20 DQ39 AA17 sdram_dq[39] 21 Vss GND 22 Vss GND 23 DQMB0 Y12 sdram_dqm[0] sdram_dqm[0] 24 DQMB4 D17 sdram_dqm[4] sdram_dqm[4] 25 DQMB1 T12 sdram_dqm[1] sdram_dqm[1] 26 DQMB5 C17 sdram_dqm[5] sdram_dqm[5] 27 Vdd +3.3V 28 Vdd +3.3V 29 A0 U16 sdram_a[0] sdram_a[0] 30 A3 W16 sdram_a[3] sdram_a[3] 31 A1 V16 sdram_a[1] sdram_a[1] 32 A4 V15 sdram_a[4] sdram_a[4] 33 A2 U15 sdram_a[2] sdram_a[2] 34 A5 Y16 sdram_a[5] sdram_a[5] 35 Vss GND 36 Vss GND 37 DQ8 R17 sdram_dq[8] sdram_dq[8] 38 DQ40 AA18 sdram_dq[40] 39 DQ9 Y20 sdram_dq[9] sdram_dq[9] 40 DQ41 AB21 sdram_dq[41] 41 DQ10 T17 sdram_dq[10] sdram_dq[10] 42 DQ42 AA8 sdram_dq[42] 43 DQ11 P16 sdram_dq[11] sdram_dq[11] 44 DQ43 AB7 sdram_dq[43] 45 Vdd +3.3V 46 Vdd +3.3V 47 DQ12 AA3 sdram_dq[12] sdram_dq[12] 48 DQ44 AA7 sdram_dq[44] 49 DQ13 W2 sdram_dq[13] sdram_dq[13] 50 DQ45 AB6 sdram_dq[45] 51 DQ14 Y2 sdram_dq[14] sdram_dq[14] 52 DQ46 AA6 sdram_dq[46] 53 DQ15 Y4 sdram_dq[15] sdram_dq[15] 54 DQ47 AB17 sdram_dq[47] 55 Vss GND 56 Vss GND 57 NC NC 58 NC NC 59 NC NC 60 NC NC 61 CK0 U5 pin 17 (Clk from APEX) 62 CKE0 T13 sdram_cke0 sdram_cke0 63 Vdd +3.3V 64 Vdd +3.3V 65 RAS E16 sdram_ras_n sdram_ras_n 66 CAS R12 sdram_cas_n sdram_cas_n 67 WE C15 sdram_we_n sdram_we_n 68 CKE1 Y13 sdram_cke1 sdram_cke1 69 S0 C16 sdram_s0_n sdram_s0_n 70 A12 W14 sdram_a[12] sdram_a[12] 71 S1 D16 sdram_s1_n sdram_s1_n 72 A13 P12 sdram_a[13] sdram_a[13] 73 NU V13 sdram_dnu sdram_dnu 74 CK1 U5 pin 19 (Clk from APEX) 75 Vss GND 76 Vss GND 77 NC NC 78 NC NC 79 NC NC 80 NC NC 81 Vdd +3.3V 82 Vdd +3.3V 83 DQ16 W5 sdram_dq[16] sdram_dq[16] 84 DQ48 AA14 sdram_dq[48] 85 DQ17 W21 sdram_dq[17] sdram_dq[17] 86 DQ49 AA15 sdram_dq[49] 87 DQ18 W22 sdram_dq[18] sdram_dq[18] 88 DQ50 AB18 sdram_dq[50] 89 DQ19 Y21 sdram_dq[19] sdram_dq[19] 90 DQ51 AA16 sdram_dq[51] 91 Vss GND 92 Vss GND 93 DQ20 W19 sdram_dq[20] sdram_dq[20] 94 DQ52 AA9 sdram_dq[52] 95 DQ21 V20 sdram_dq[21] sdram_dq[21] 96 DQ53 AB8 sdram_dq[53] 97 DQ22 W1 sdram_dq[22] sdram_dq[22] 98 DQ54 AA10 sdram_dq[54] 99 DQ23 AB2 sdram_dq[23] sdram_dq[23] 100 DQ55 AA11 sdram_dq[55] 101 Vdd +3.3V 102 Vdd +3.3V 103 A6 W15 sdram_a[6] sdram_a[6] 104 A7 T14 sdram_a[7] sdram_a[7] 105 A8 Y15 sdram_a[8] sdram_a[8] 106 BA0 Y14 sdram_ba[0] sdram_ba[0] 107 Vss GND 108 Vss GND 109 A9 R13 sdram_a[9] sdram_a[9] 110 BA1 U13 sdram_ba[1] sdram_ba[1] 111 A10/AP U14 sdram_a[10] sdram_a[10] 112 A11 V14 sdram_a[11] sdram_a[11] 113 Vdd +3.3V 114 Vdd +3.3V 115 DQMB2 Y11 sdram_dqm[2] sdram_dqm[2] 116 DQMB6 H16 sdram_dqm[6] sdram_dqm[6] 117 DQMB3 E17 sdram_dqm[3] sdram_dqm[3] 118 DQMB7 F16 sdram_dqm[7] sdram_dqm[7] 119 Vss GND 120 Vss GND 121 DQ24 V1 sdram_dq[24] sdram_dq[24] 122 DQ56 AA12 sdram_dq[56] 123 DQ25 Y1 sdram_dq[25] sdram_dq[25] 124 DQ57 AB15 sdram_dq[57] 125 DQ26 V2 sdram_dq[26] sdram_dq[26] 126 DQ58 AB16 sdram_dq[58] 127 DQ27 Y22 sdram_dq[27] sdram_dq[27] 128 DQ59 AA13 sdram_dq[59] 129 Vdd +3.3V 130 Vdd +3.3V 131 DQ28 AA20 sdram_dq[28] sdram_dq[28] 132 DQ60 Y5 sdram_dq[60] 133 DQ29 AA19 sdram_dq[29] sdram_dq[29] 134 DQ61 Y6 sdram_dq[61] 135 DQ30 V21 sdram_dq[30] sdram_dq[30] 136 DQ62 T6 sdram_dq[62] 137 DQ31 V22 sdram_dq[31] sdram_dq[31] 138 DQ63 P7 sdram_dq[63] 139 Vss GND 140 Vss GND 141 SDA W6 sdram_sda sdram_sda 142 SCL W7 sdram_scl sdram_scl 143 Vdd +3.3V 144 Vdd +3.3V