-- Case Clause Check

-- (C)2001-2002 Kiyoaki Hoshino
-- (C)Kesakoy Laboratory, Osaka Institute of Technology
-- hoshino@kesakoy.elc.oit.ac.jp

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY casecheck IS
	PORT
	(
		clk			: IN	std_logic;
		abcd		: IN	std_logic_vector(3 downto 0);
		f			: OUT	std_logic
	);
END casecheck;

ARCHITECTURE rtl OF casecheck IS
BEGIN
	PROCESS (clk)
	BEGIN
		IF (clk'EVENT AND clk = '1') THEN
			case ( abcd ) is
			when "0000" =>	f <= '0';
			when "0001" =>	f <= '1';
			when "0010" =>	f <= '0';
			when "0011" =>	f <= '0';
			when "0100" =>	f <= '0';
			when "0101" =>	f <= '1';
			when "0110" =>	f <= '0';
			when "0111" =>	f <= 'X';
			when "1000" =>	f <= '0';
			when "1001" =>	f <= 'X';
			when "1010" =>	f <= '0';
			when "1011" =>	f <= '1';
			when "1100" =>	f <= '1';
			when "1101" =>	f <= 'X';
			when "1110" =>	f <= '1';
			when "1111" =>	f <= 'X';
			when others =>	f <= 'X';
			end case;		END IF;
	END PROCESS;
END rtl;