Sazanami Online

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Index に戻る

ＭＥＮＵ

・PC-CARD

・CardBus

・PC-CARD

・PCMCIA

・CompactFlash

・拡張バス

・ISA バス

・PCI バス

・AGP バス

・メモリ

・72pin SIMM

・72pin so-DIMM

・144pin DIMM

・168pin DIMM

・ROM

・3-wire シリアルEEPROM

・I2C シリアルEEPROM

・DIP32pin FLASH/EPROM

・DIP28pin EPROM

PC-CARD

CARD BUS

ピン定義内容
1 GND Ground
2 CAD0 Address/Data 0
3 CAD1 Address/Data 1
4 CAD3 Address/Data 3
5 CAD5 Address/Data 5
6 CAD7 Address/Data 7
7 CCBE0# Command/Byte Enable 0
8 CAD9 Address/Data 9
9 CAD11 Address/Data 11
10 CAD12 Address/Data 12
11 CAD14 Address/Data 14
12 CCBE1# Command/Byte Enable 1
13 CPAR Parity
14 CPERR# Parity error
15 CGNT# Grant
16 CINT# Interrupt
17 Vcc Vcc
18 Vpp1 Vpp1
19 CCLK CCLK
20 CIRDY# Initiator Ready
21 CCBE2# Command/Byte Enable 2
22 CAD18 Address/Data 18
23 CAD20 Address/Data 20
24 CAD21 Address/Data 21
25 CAD22 Address/Data 22
26 CAD23 Address/Data 23
27 CAD24 Address/Data 24
28 CAD25 Address/Data 25
29 CAD26 Address/Data 26
30 CAD27 Address/Data 27
31 CAD29 Address/Data 29
32 RSRVD Reserved
33 CCLKRUN# CCLKRUN#
34 GND Ground
35 GND Ground
36 CCD1# Card Detect 1
37 CAD2 Address/Data 2
38 CAD4 Address/Data 4
39 CAD6 Address/Data 6
40 RSRVD Reserved
41 CAD8 Address/Data 8
42 CAD10 Address/Data 10
43 CVS1
44 CAD13 Address/Data 13
45 CAD15 Address/Data 15
46 CAD16 Address/Data 16
47 RSRVD Reserved
48 CBLOCK# Block ???
49 CSTOP# Stop transfer cycle
50 CDEVSEL# Device Select
51 Vcc Vcc
52 Vpp2 Vpp2
53 CTRDY# Target Ready
54 CFRAME# Address or Data phase
55 CAD17 Address/Data 17
56 CAD19 CAD19
57 CVS2
58 CRST# Reset
59 CSERR# System Error
60 CREQ# Request ???
61 CCBE3# Command/Byte Enable 3
62 CAUDIO Audio ???
63 CSTSCHG
64 CAD28 Address/Data 28
65 CAD30 Address/Data 30
66 CAD31 Address/Data 31
67 CCD2# Card Detect 2
68 GND Ground

PC　CARD

Pin Memory I/O+Mem Description
1 GND GND Ground
2 D3 D3 Data 3
3 D4 D4 Data 4
4 D5 D5 Data 5
5 D6 D6 Data 6
6 D7 D7 Data 7
7 CE1# CE1#
8 A10 A10 Address 10
9 OE# OE# Output Enable
10 A11 A11 Address 11
11 A9 A9 Address 9
12 A8 A8 Address 8
13 A13 A13 Address 13
14 A14 A14 Address 14
15 WE# WE# Write Enable ???
16 READY IREQ#
17 Vcc Vcc Vcc
18 Vpp1 Vpp1 Vpp1
19 A16 A16 Address 16
20 A15 A15 Address 15
21 A12 A12 Address 12
22 A7 A7 Address 7
23 A6 A6 Address 6
24 A5 A5 Address 5
25 A4 A4 Address 4
26 A3 A3 Address 3
27 A2 A2 Address 2
28 A1 A1 Address 1
29 A0 A0 Address 0
30 D0 D0 Data 0
31 D1 D1 Data 1
32 D2 D2 Data 2
33 WP IOIS16#
34 GND GND Ground
35 GND GND Ground
36 CD1# CD1# Card Detect 1
37 D11 D11 Data 11
38 D12 D12 Data 12
39 D13 D13 Data 13
40 D14 D14 Data 14
41 D15 D15 Data 15
42 CE2# CE2#
43 VS1# VS1#
44 RSRVD IORD# Reserved / IORD#
45 RSRVD IOWR# Reserved / IOWR#
46 A17 A17 Address 17
47 A18 A18 Address 18
48 A19 A19 Address 19
49 A20 A20 Address 20
50 A21 A21 Address 21
51 Vcc Vcc Vcc
52 Vpp2 Vpp2 Vpp2
53 A22 A22 Address 22
54 A23 A23 Address 23
55 A24 A24 Address 24
56 A25 A25 Address 25
57 VS2# VS2#
58 RESET RESET Reset
59 WAIT# WAIT#
60 RSRVD INPACK# Reserved / ???
61 REG# REG#
62 BVD2 SPKR# Battery Voltage 2 / Speaker ???
63 BVD1 STSCHG# Battery Voltage 1 / ???
64 D8 D8 Data 8
65 D9 D9 Data 9
66 D10 D10 Data 10
67 CD2# CD2#
68 GND GND Ground

PCMCIA

Pin Name Dir Description
1 GND Ground
2 D3 I/O Data 3
3 D4 I/O Data 4
4 D5 I/O Data 5
5 D6 I/O Data 6
6 D7 I/O Data 7
7 /CE1 O Card Enable 1
8 A10 O Address 10
9 /OE O Output Enable
10 A11 O Address 11
11 A9 O Address 9
12 A8 O Address 8
13 A13 O Address 13
14 A14 O Address 14
15 /WE:/P O Write Enable : Program
16 /READY:/IREQ I Ready : Busy (IREQ)
17 VCC O +5V
18 VPP1 O Programming Voltage (EPROM)
19 A16 O Address 16
20 A15 O Address 15
21 A12 O Address 12
22 A7 O Address 7
23 A6 O Address 6
24 A5 O Address 5
25 A4 O Address 4
26 A3 O Address 3
27 A2 O Address 2
28 A1 O Address 1
29 A0 O Address 0
30 D0 I/O Data 0
31 D1 I/O Data 1
32 D2 I/O Data 2
33 /WP:/IOIS16 I Write Protect : IOIS16
34 GND Ground
35 GND Ground
36 /CD1 I Card Detect 1
37 D11 I/O Data 11
38 D12 I/O Data 12
39 D13 I/O Data 13
40 D14 I/O Data 14
41 D15 I/O Data 15
42 /CE2 O Card Enable 2
43 /VS1 O Refresh
44 /IORD ? I/O Read
45 /IOWR ? I/O Write
46 A17 O Address 17
47 A18 O Address 18
48 A19 O Address 19
49 A20 O Address 20
50 A21 O Address 21
51 VCC O +5V
52 VPP2 O Programmeing Voltage 2 (EPROM)
53 A22 O Address 22
54 A23 O Address 23
55 A24 O Address 24
56 A25 O Address 25
57 /VS2 ? RFU
58 RESET ? RESET
59 /WAIT ? WAIT
60 /INPACK ?
61 /REG O Register Select
62 /BVD2:SPKR I Battery Voltage Detect 2 : SPKR
63 /BVD1:STSCHG I Battery Voltage Detect 1 : STSCHG
64 D8 I/O Data 8
65 D9 I/O Data 9
66 D10 I/O Data 10
67 /CD2 I Card Detect 2
68 GND Ground

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CompactFlash

Pin Name Description
1 GND Ground
2 D3 Data 3
3 D4 Data 4
4 D5 Data 5
5 D6 Data 6
6 D7 Data 7
7 /CE1 Card Enable 1
8 A10 Address 10
9 /OE Output Enable
10 A9 Address 9
11 A8 Address 8
12 A7 Address 7
13 VCC +5V
14 A6 Address 6
15 A5 Address 5
16 A4 Address 4
17 A3 Address 3
18 A2 Address 2
19 A1 Address 1
20 A0 Address 0
21 D0 Data 0
22 D1 Data 1
23 D2 Data 2
24 /WP:/IOIS16 Write Protect : IOIS16
25 /CD2 Card Detect 2

Pin Name Description
26 /CD1 Card Detect 1
27 D11 Data 11
28 D12 Data 12
29 D13 Data 13
30 D14 Data 14
31 D15 Data 15
32 /CE2 Card Enable 2
33 /VS1 Refresh
34 /IORD I/O Read
35 /IOWR I/O Write
36 /WE Write Enable
37 /READY:/RDY:/IREQ Ready : Busy : IREQ
38 VCC +5V
39 CSEL �
40 /VS2 RFU
41 RESET Reset
42 /WAIT Wait
43 /INPACK �
44 /REG Register Select
45 /BVD2:SPKR Battery Voltage Detect 2 : SPKR
46 /BVD1:STSCHG Battery Voltage Detect 1 : STSCHG
47 D8 Data 8
48 D9 Data 9
49 D10 Data 10
50 GND Ground

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拡張バス

ISAバス

ピン定義 I/O 意味
A1 /I/O CH CK I I/O channel check; active low=parity error
A2 D7 I/O Data bit 7
A3 D6 I/O Data bit 6
A4 D5 I/O Data bit 5
A5 D4 I/O Data bit 4
A6 D3 I/O Data bit 3
A7 D2 I/O Data bit 2
A8 D1 I/O Data bit 1
A9 D0 I/O Data bit 0
A10 I/O CH RDY I I/O Channel ready, pulled low to lengthen memory cycles
A11 AEN O Address enable; active high when DMA controls bus
A12 A19 O Address bit 19
A13 A18 O Address bit 18
A14 A17 O Address bit 17
A15 A16 O Address bit 16
A16 A15 O Address bit 15
A17 A14 O Address bit 14
A18 A13 O Address bit 13
A19 A12 O Address bit 12
A20 A11 O Address bit 11
A21 A10 O Address bit 10
A22 A9 O Address bit 9
A23 A8 O Address bit 8
A24 A7 O Address bit 7
A25 A6 O Address bit 6
A26 A5 O Address bit 5
A27 A4 O Address bit 4
A28 A3 O Address bit 3
A29 A2 O Address bit 2
A30 A1 O Address bit 1
A31 A0 O Address bit 0

C1 SBHE I/O System bus high enable (data available on SD8-15)
C2 LA23 I/O Address bit 23
C3 LA22 I/O Address bit 22
C4 LA21 I/O Address bit 21
C5 LA20 I/O Address bit 20
C6 LA18 I/O Address bit 19
C7 LA17 I/O Address bit 18
C8 LA16 I/O Address bit 17
C9 /MEMR I/O Memory Read (Active on all memory read cycles)
C10 /MEMW I/O Memory Write (Active on all memory write cycles)
C11 SD08 I/O Data bit 8
C12 SD09 I/O Data bit 9
C13 SD10 I/O Data bit 10
C14 SD11 I/O Data bit 11
C15 SD12 I/O Data bit 12
C16 SD13 I/O Data bit 13
C17 SD14 I/O Data bit 14
C18 SD15 I/O Data bit 15

ピン定義 I/O 意味
B1 GND Ground
B2 RESET O Active high to reset or initialize system logic
B3 +5V +5 VDC
B4 IRQ2 I Interrupt Request 2
B5 -5VDC -5 VDC
B6 DRQ2 I DMA Request 2
B7 -12VDC -12 VDC
B8 /NOWS I No WaitState
B9 +12VDC +12 VDC
B10 GND Ground
B11 /SMEMW O System Memory Write
B12 /SMEMR O System Memory Read
B13 /IOW O I/O Write
B14 /IOR O I/O Read
B15 /DACK3 O DMA Acknowledge 3
B16 DRQ3 I DMA Request 3
B17 /DACK1 O DMA Acknowledge 1
B18 DRQ1 I DMA Request 1
B19 /REFRESH I/O Refresh
B20 CLOCK O System Clock (67 ns, 8-8.33 MHz, 50% duty cycle)
B21 IRQ7 I Interrupt Request 7
B22 IRQ6 I Interrupt Request 6
B23 IRQ5 I Interrupt Request 5
B24 IRQ4 I Interrupt Request 4
B25 IRQ3 I Interrupt Request 3
B26 /DACK2 O DMA Acknowledge 2
B27 T/C O Terminal count; pulses high when DMA term. count reached
B28 ALE O Address Latch Enable
B29 +5V +5 VDC
B30 OSC O High-speed Clock (70 ns, 14.31818 MHz, 50% duty cycle)
B31 GND Ground

D1 /MEMCS16 I Memory 16-bit chip select (1 wait, 16-bit memory cycle)
D2 /IOCS16 I I/O 16-bit chip select (1 wait, 16-bit I/O cycle)
D3 IRQ10 I Interrupt Request 10
D4 IRQ11 I Interrupt Request 11
D5 IRQ12 I Interrupt Request 12
D6 IRQ15 I Interrupt Request 15
D7 IRQ14 I Interrupt Request 14
D8 /DACK0 O DMA Acknowledge 0
D9 DRQ0 I DMA Request 0
D10 /DACK5 O DMA Acknowledge 5
D11 DRQ5 I DMA Request 5
D12 /DACK6 O DMA Acknowledge 6
D13 DRQ6 I DMA Request 6
D14 /DACK7 O DMA Acknowledge 7
D15 DRQ7 I DMA Request 7
D16 +5 V
D17 /MASTER I Used with DRQ to gain control of system
D18 GND Ground

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PCI バス

ピン +5V +3.3V Universal 定義
A1 TRST � � Test Logic Reset
A2 +12V � � +12 VDC
A3 TMS � � Test Mde Select
A4 TDI � � Test Data Input
A5 +5V � � +5 VDC
A6 INTA � � Interrupt A
A7 INTC � � Interrupt C
A8 +5V � � +5 VDC
A9 RESV01 � � Reserved VDC
A10 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
A11 RESV03 � � Reserved VDC
A12 GND03 (OPEN) (OPEN) Ground or Open (Key)
A13 GND05 (OPEN) (OPEN) Ground or Open (Key)
A14 RESV05 � � Reserved VDC
A15 RESET � � Reset
A16 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
A17 GNT � � Grant PCI use
A18 GND08 � � Ground
A19 RESV06 � � Reserved VDC
A20 AD30 � � Address/Data 30
A21 +3.3V01 � � +3.3 VDC
A22 AD28 � � Address/Data 28
A23 AD26 � � Address/Data 26
A24 GND10 � � Ground
A25 AD24 � � Address/Data 24
A26 IDSEL � � Initialization Device Select
A27 +3.3V03 � � +3.3 VDC
A28 AD22 � � Address/Data 22
A29 AD20 � � Address/Data 20
A30 GND12 � � Ground
A31 AD18 � � Address/Data 18
A32 AD16 � � Address/Data 16
A33 +3.3V05 � � +3.3 VDC
A34 FRAME � � Address or Data phase
A35 GND14 � � Ground
A36 TRDY � � Target Ready
A37 GND15 � � Ground
A38 STOP � � Stop Transfer Cycle
A39 +3.3V07 � � +3.3 VDC
A40 SDONE � � Snoop Done
A41 SBO � � Snoop Backoff
A42 GND17 � � Ground
A43 PAR � � Parity
A44 AD15 � � Address/Data 15
A45 +3.3V10 � � +3.3 VDC
A46 AD13 � � Address/Data 13
A47 AD11 � � Address/Data 11
A48 GND19 � � Ground
A49 AD9 � � Address/Data 9
� � � � �
� � � � �
A52 C/BE0 � � Command, Byte Enable 0
A53 +3.3V11 � � +3.3 VDC
A54 AD6 � � Address/Data 6
A55 AD4 � � Address/Data 4
A56 GND21 � � Ground
A57 AD2 � � Address/Data 2
A58 AD0 � � Address/Data 0
A59 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
A60 REQ64 � � Request 64 bit ???
A61 VCC11 � � +5 VDC
A62 VCC13 � � +5 VDC
� � � � �
A63 GND � � Ground
A64 C/BE[7]# � � Command, Byte Enable 7
A65 C/BE[5]# � � Command, Byte Enable 5
A66 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
A67 PAR64 � � Parity 64 ???
A68 AD62 � � Address/Data 62
A69 GND � � Ground
A70 AD60 � � Address/Data 60
A71 AD58 � � Address/Data 58
A72 GND � � Ground
A73 AD56 � � Address/Data 56
A74 AD54 � � Address/Data 54
A75 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
A76 AD52 � � Address/Data 52
A77 AD50 � � Address/Data 50
A78 GND � � Ground
A79 AD48 � � Address/Data 48
A80 AD46 � � Address/Data 46
A81 GND � � Ground
A82 AD44 � � Address/Data 44
A83 AD42 � � Address/Data 42
A84 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
A85 AD40 � � Address/Data 40
A86 AD38 � � Address/Data 38
A87 GND � � Ground
A88 AD36 � � Address/Data 36
A89 AD34 � � Address/Data 34
A90 GND � � Ground
A91 AD32 � � Address/Data 32
A92 RES � � Reserved
A93 GND � � Ground
A94 RES � � Reserved
� � � � �

ピン +5V +3.3V Universal 定義
B1 -12V � � -12 VDC
B2 TCK � � Test Clock
B3 GND � � Ground
B4 TDO � � Test Data Output
B5 +5V � � +5 VDC
B6 +5V � � +5 VDC
B7 INTB � � Interrupt B
B8 INTD � � Interrupt D
B9 PRSNT1 � � Reserved
B10 RES � � +V I/O (+5 V or +3.3 V)
B11 PRSNT2 � � ??
B12 GND (OPEN) (OPEN) Ground or Open (Key)
B13 GND (OPEN) (OPEN) Ground or Open (Key)
B14 RES � � Reserved VDC
B15 GND � � Reset
B16 CLK � � Clock
B17 GND � � Ground
B18 REQ � � Request
B19 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
B20 AD31 � � Address/Data 31
B21 AD29 � � Address/Data 29
B22 GND � � Ground
B23 AD27 � � Address/Data 27
B24 AD25 � � Address/Data 25
B25 +3.3V � � +3.3VDC
B26 C/BE3 � � Command, Byte Enable 3
B27 AD23 � � Address/Data 23
B28 GND � � Ground
B29 AD21 � � Address/Data 21
B30 AD19 � � Address/Data 19
B31 +3.3V � � +3.3 VDC
B32 AD17 � � Address/Data 17
B33 C/BE2 � � Command, Byte Enable 2
B34 GND13 � � Ground
B35 IRDY � � Initiator Ready
B36 +3.3V06 � � +3.3 VDC
B37 DEVSEL � � Device Select
B38 GND16 � � Ground
B39 LOCK � � Lock bus
B40 PERR � � Parity Error
B41 +3.3V08 � � +3.3 VDC
B42 SERR � � System Error
B43 +3.3V09 � � +3.3 VDC
B44 C/BE1 � � Command, Byte Enable 1
B45 AD14 � � Address/Data 14
B46 GND18 � � Ground
B47 AD12 � � Address/Data 12
B48 AD10 � � Address/Data 10
B49 GND20 � � Ground
B50 (OPEN) GND (OPEN) Ground or Open (Key)
B51 (OPEN) GND (OPEN) Ground or Open (Key)
B52 AD8 � � Address/Data 8
B53 AD7 � � Address/Data 7
B54 +3.3V12 � � +3.3 VDC
B55 AD5 � � Address/Data 5
B56 AD3 � � Address/Data 3
B57 GND22 � � Ground
B58 AD1 � � Address/Data 1
B59 VCC08 � � +5 VDC
B60 ACK64 � � Acknowledge 64 bit ???
B61 VCC10 � � +5 VDC
B62 VCC12 � � +5 VDC

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AGP バス

ピン定義
A1 +12 V dc
A2 spare
A3 Reserved* Ground
A4 USB-
A5 Ground
A6 INTA#
A7 RST#
A8 GNT#
A9 VCC 3.3
A10 ST1
A11 Reserved
A12 PIPE#
A13 Ground
A14 Spare
A15 SBA1
A16 VCC 3.3
A17 SBA3
A18 Reserved
A19 Ground
A20 SBA5
A21 SBA7
A22 Key
A23 Key
A24 Key
A25 Key
A26 AD30
A27 AD28
A28 VCC 3.3
A29 AD26
A30 AD24
A31 Ground
A32 Reserved
A33 C/BE3#
A34 Vddq 3.3
A35 AD22
A36 AD20
A37 Ground
A38 AD18
A39 AD16
A40 Vddq 3.3
A41 FRAME#
A42 Spare
A43 Ground
A44 Spare
A45 VCC 3.3
A46 TRDY#
A47 STOP#
A48 Spare
A49 Ground
A50 PAR
A51 AD15
A52 Vddq 3.3
A53 AD13
A54 AD11
A55 Ground
A56 AD9
A57 C/BE0#
A58 Vddq 3.3
A59 Reserved
A60 AD6
A61 Ground
A62 AD4
A63 AD2
A64 Vddq 3.3
A65 AD0
A66 SMB1

ピン定義
B1 spare
B2 +5 V dc
B3 +5 V dc
B4 USB+
B5 Ground
B6 INTB#
B7 CLK
B8 REQ#
B9 VCC 3.3
B10 ST0
B11 ST2
B12 RBF#
B13 Ground
B14 Spare
B15 SBA0
B16 VCC 3.3
B17 SBA2
B18 SB_STB
B19 Ground
B20 SBA4
B21 SBA6
B22 Key
B23 Key
B24 Key
B25 Key
B26 AD31
B27 AD29
B28 VCC 3.3
B29 AD27
B30 AD25
B31 Ground
B32 AD STB1
B33 AD23
B34 Vddq 3.3
B35 AD21
B36 AD19
B37 Ground
B38 AD17
B39 C/BE2#
B40 Vddq 3.3
B41 IRDY#
B42 Spare
B43 Ground
B44 Spare
B45 VCC 3.3
B46 DEVSEL#
B47 Vddq 3.3
B48 PERR#
B49 Ground
B50 SERR#
B51 C/BE1#
B52 Vddq 3.3
B53 AD14
B54 AD12
B55 Ground
B56 AD10
B57 AD8
B58 Vddq 3.3
B59 AD STB0
B60 AD7
B61 Ground
B62 AD5
B63 AD3
B64 Vddq 3.3
B65 AD1
B66 SMB0

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メモリ

72pin SIMM

ピン Non-P Parity ピン Non-P Parity
1 VSS 2 DQ0
3 DQ16 4 DQ1
5 DQ17 6 DQ2
7 DQ18 8 DQ3
9 DQ19 10 VCC
11 PD5 12 A0
13 A1 14 A2
15 A3 16 A4
17 A5 18 A6
19 A10 20 DQ4
21 DQ20 22 DQ5
23 DQ21 24 DQ6
25 DQ22 26 DQ7
27 DQ23 28 A7
29 A11 30 VCC
31 A8 32 A9
33 /RAS3 34 /RAS2
35 n/c PQ3 36 n/c PQ1
37 n/c PQ2 38 n/c PQ4
39 VSS 40 /CAS0
41 /CAS2 42 /CAS3
43 /CAS1 44 /RAS0
45 /RAS1 46
47 /WE 48 (/ECC)
49 DQ8 50 DQ24
51 DQ9 52 DQ25
53 DQ10 54 DQ26
55 DQ11 56 DQ27
57 DQ12 58 DQ28
59 VCC 60 DQ29
61 DQ13 62 DQ30
63 DQ14 64 DQ31
65 DQ16 66 PD2
67 PD1 PD2
69 PD3 PD4
71 72 VSS

72pin SIMM : Size

PD1 PD2 PD5 Size
NC NC NC 8 or 128MB
GND NC NC 1 or 16MB
NC GND NC 2 or 32MB
GND GND NC 4 or 64MB
GND NC GND 16 or 256MB
NC GND GND 32 or 512MB

72pin SIMM : Accesstime

PD3 PD4 Accesstime
GND GND 50, 100 ns
NC GND 80 ns
GND NC 70 ns
NC NC 60 ns

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72pin so-DIMM

ピン Non-P Parity ピン Non-P Parity
1 VSS 2 DQ0
3 DQ16 4 DQ1
5 DQ17 6 DQ2
7 DQ18 8 DQ3
9 DQ19 10 VCC
11 PD1 12 A0
13 A1 14 A2
15 A3 16 A4
17 A5 18 A6
19 A10 20 DQ4
21 DQ20 22 DQ5
23 DQ21 24 DQ6
25 DQ22 26 DQ7
27 DQ23 28 A7
29 A11 30 VCC
31 A8 32 A9
33 /RAS3 34 /RAS2
35 n/c PQ3 36 n/c PQ1
37 n/c PQ2 38 n/c PQ4
39 VSS 40 /CAS0
41 /CAS2 42 /CAS3
43 /CAS1 44 /RAS0
45 /RAS1 46
47 /WE 48 (/ECC)
49 DQ8 50 DQ24
51 DQ9 52 DQ25
53 DQ10 54 DQ26
55 DQ11 56 DQ27
57 DQ12 58 DQ28
59 VCC 60 DQ29
61 DQ13 62 DQ30
63 DQ14 64 DQ31
65 DQ16 66 PD2
67 PD3 68 PD4
69 PD5 70 PD6
71 PD7 72 VSS

72pin so-DIMM : Size

PD1 PD2 PD3 PD4 MOD Device Row Col
NC GND GND NC 1M x 32bit 1Mx2/4 16/18 10 10
NC GND NC NC 1M x 32bit 1Mx16/18 12 8
NC GND GND GND 2M x 32bit 1Mx2/4 16/18 10 10
NC GND NC GND 2M x 32bit 1Mx16/18 12 8
GND NC GND NC 2M x 32bit 2Mx8/9 11 10
GND NC GND GND 4M x 32bit 2Mx8/9 11 10
NC NC GND NC 4M x 32bit 4Mx2/4 16/18 12
11 10
11
NC NC GND GND 8M x 32bit 4Mx2/4 16/18 12
11 10
11
GND GND NC NC 8M x 32bit 8Mx8/9 12 11
GND GND NC GND 16M x 32bit 8Mx8/9 12 11
GND NC NC NC 16M x 32bit 16Mx2/4 13 11

72pin so-DIMM : Accesstime

PD5
PD6 Accesstime
GND GND 50, 100 ns
NC GND 80 ns
GND NC 70 ns
NC NC 60 ns

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144pin DIMM

ピン種別定義ピン種別定義
Normal ECC SDRAM Normal ECC SDRAM
1 Vss 2 Vss
3 DQ0 4 DQ32
5 DQ1 6 DQ33
7 DQ2 8 DQ34
9 DQ3 10 DQ35
11 Vdd 12 Vdd
13 DQ4 14 DQ36
15 DQ5 16 DQ37
17 DQ6 18 DQ38
19 DQ7 20 DQ39
21 Vss 22 Vss
23 /CAS0 DQM0 24 /CAS4 DQM4
25 /CAS1 DQM1 26 /CAS5 DQM5
27 Vdd 28 Vdd
29 A0 30 A3
31 A1 32 A4
33 A2 34 A5
35 Vss 36 Vss
37 DQ8 38 DQ40
39 DQ9 40 DQ41
41 DQ10 42 DQ42
43 DQ11 44 DQ43
45 Vdd 46 Vdd
47 DQ12 48 DQ44
49 DQ13 50 DQ45
51 DQ14 52 DQ46
53 DQ15 54 DQ47
55 Vss 56 Vss
57 NC CB0 NC 58 NC CB4 NC
59 NC CB1 NC 60 NC CB5 NC
61 DU CLK0 62 DU CKE0
63 Vdd 64 Vdd
65 DU /RAS 66 DU /CAS
67 /WE 68 NC CKE1
69 /RAS0 /CS0 70 NC *A12
71 /RAS1 /CS1 72 NC *A13

ピン種別定義ピン種別定義
Normal ECC SDRAM Normal ECC SDRAM
73 /OE DU 74 NC CLK1
75 Vss 76 Vss
77 NC CB2 NC 78 NC CB6 NC
79 NC CB3 NC 80 NC CB7 NC
81 Vdd 82 Vdd
83 DQ16 84 DQ48
85 DQ17 86 DQ49
87 DQ18 88 DQ50
89 DQ19 90 DQ51
91 Vss 92 Vss
93 DQ20 94 DQ52
95 DQ21 96 DQ53
97 DQ22 98 DQ54
99 DQ23 100 DQ55
101 Vdd 102 Vdd
103 A6 104 A7
105 A8 106 A11 BA0
107 Vss 108 Vss
109 A9 110 A12 BA1
111 A10 A10/AP 112 A13 A11
113 Vdd 114 Vdd
115 /CAS2 DQM2 116 /CAS6 DQM6
117 /CAS3 DQM3 118 /CAS7 DQM7
119 Vss 120 Vss
121 DQ24 122 DQ56
123 DQ25 124 DQ57
125 DQ26 126 DQ58
127 DQ27 128 DQ59
129 Vdd 130 Vdd
131 DQ28 132 DQ60
133 DQ29 134 DQ61
135 DQ30 136 DQ62
137 DQ31 138 DQ63
139 Vss 140 Vss
141 SDA 142 SCL
143 Vdd 144 Vdd

SPD Serial WP,SA0-SA2はGND接続.

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168pin DIMM

ピン種別定義意味
Non-P 72 ECC 80 ECC
1 VSS VSS VSS Ground
2 DQ0 DQ0 DQ0 Data 0
3 DQ1 DQ1 DQ1 Data 1
4 DQ2 DQ2 DQ2 Data 2
5 DQ3 DQ3 DQ3 Data 3
6 VDD VDD VDD +5 VDC or +3.3 VDC
7 DQ4 DQ4 DQ4 Data 4
8 DQ5 DQ5 DQ5 Data 5
9 DQ6 DQ6 DQ6 Data 6
10 DQ7 DQ7 DQ7 Data 7
11 DQ8 DQ8 DQ8 Data 8
12 VSS VSS VSS Ground
13 DQ9 DQ9 DQ9 Data 9
14 DQ10 DQ10 DQ10 Data 10
15 DQ11 DQ11 DQ11 Data 11
16 DQ12 DQ12 DQ12 Data 12
17 DQ13 DQ13 DQ13 Data 13
18 VDD VDD VDD +5 VDC or +3.3 VDC
19 DQ14 DQ14 DQ14 Data 14
20 DQ15 DQ15 DQ15 Data 15
21 n/c CB0 CB0 Parity/Check Bit Input/Output 0
22 n/c CB1 CB1 Parity/Check Bit Input/Output 01
23 VSS VSS VSS Ground
24 n/c n/c CB8 Parity/Check Bit Input/Output 8
25 n/c n/c CB9 Parity/Check Bit Input/Output 9
26 VDD VDD VDD +5 VDC or +3.3 VDC
27 /WE /WE /WE Read/Write
28 DQMB0 DQMB0 DQMB0 Byte Mask signal 0
29 DQMB1 DQMB1 DQMB1 Byte Mask signal 1
30 /S0 /S0 /S0 Chip Select 0
31 DU DU DU Don't Use
32 VSS VSS VSS Ground
33 A0 A0 A0 Address 0
34 A2 A2 A2 Address 2
35 A4 A4 A4 Address 4
36 A6 A6 A6 Address 6
37 A8 A8 A8 Address 8
38 A10/AP A10/AP A10/AP Address 10
39 BA1 BA1 BA1 Bank Address 1
40 VDD VDD VDD +5 VDC or +3.3 VDC
41 VDD VDD VDD +5 VDC or +3.3 VDC
42 CK0 CK0 CK0 Clock signal 0

ピン種別定義意味
Non-P 72 ECC 80 ECC
85 VSS VSS VSS Ground
86 DQ32 DQ32 DQ32 Data 32
87 DQ33 DQ33 DQ33 Data 33
88 DQ34 DQ34 DQ34 Data 34
89 DQ35 DQ35 DQ35 Data 35
90 VDD VDD VDD +5 VDC or +3.3 VDC
91 DQ36 DQ36 DQ36 Data 36
92 DQ37 DQ37 DQ37 Data 37
93 DQ38 DQ38 DQ38 Data 38
94 DQ39 DQ39 DQ39 Data 39
95 DQ40 DQ40 DQ40 Data 40
96 VSS VSS VSS Ground
97 DQ41 DQ41 DQ41 Data 41
98 DQ42 DQ42 DQ42 Data 42
99 DQ43 DQ43 DQ43 Data 43
100 DQ44 DQ44 DQ44 Data 44
101 DQ45 DQ45 DQ45 Data 45
102 VDD VDD VDD +5 VDC or +3.3 VDC
103 DQ46 DQ46 DQ46 Data 46
104 DQ47 DQ47 DQ47 Data 47
105 n/c CB4 CB4 Parity/Check Bit Input/Output 4
106 n/c CB5 CB5 Parity/Check Bit Input/Output 5
107 VSS VSS VSS Ground
108 n/c n/c CB12 Parity/Check Bit Input/Output 12
109 n/c n/c CB13 Parity/Check Bit Input/Output 13
110 VDD VDD VDD +5 VDC or +3.3 VDC
111 /CAS /CAS /CAS Column Address Strobe
112 DQMB4 DQMB4 DQMB4 Byte Mask signal 4
113 DQMB5 DQMB5 DQMB5 �Byte Mask signal 5
114 /S1 /S1 /S1 Chip Select 1
115 /RAS /RAS /RAS Row Address Strobe
116 VSS VSS VSS Ground
117 A1 A1 A1 Address 1
118 A3 A3 A3 Address 3
119 A5 A5 A5 Address 5
120 A7 A7 A7 Address 7
121 A9 A9 A9 Address 9
122 BA0 BA0 BA0 Bank Address 0
123 A11 A11 A11 Address 11
124 VDD VDD VDD +5 VDC or +3.3 VDC
125 CK1 CK1 CK1 Clock signal 1
126 A12 A12 A12 Address 12

ピン種別定義意味
Non-P 72 ECC 80 ECC
43 VSS VSS VSS Ground
44 DU DU DU Don't Use
45 /S2 /S2 /S2 Chip Select 2
46 DQMB2 DQMB2 DQMB2 Byte Mask signal 2
47 DQMB3 DQMB3 DQMB3 Byte Mask signal 3
48 DU DU DU Don't Use
49 VDD VDD VDD +5 VDC or +3.3 VDC
50 n/c n/c CB10 Parity/Check Bit Input/Output 10
51 n/c n/c CB11 Parity/Check Bit Input/Output 11
52 n/c CB2 CB2 Parity/Check Bit Input/Output 2
53 n/c CB3 CB3 Parity/Check Bit Input/Output 3
54 VSS VSS VSS Ground
55 DQ16 DQ16 DQ16 Data 16
56 DQ17 DQ17 DQ17 Data 17
57 DQ18 DQ18 DQ18 Data 18
58 DQ19 DQ19 DQ19 Data 19
59 VDD VDD VDD +5 VDC or +3.3 VDC
60 DQ20 DQ20 DQ20 Data 20
61 n/c n/c n/c Not connected
62 Vref,NC Vref,NC Vref,NC �
63 CKE1 CKE1 CKE1 Clock Enable Signal 1
64 VSS VSS VSS Ground
65 DQ21 DQ21 DQ21 Data 21
66 DQ22 DQ22 DQ22 Data 22
67 DQ23 DQ23 DQ23 Data 23
68 VSS VSS VSS Ground
69 DQ24 DQ24 DQ24 Data 24
70 DQ25 DQ25 DQ25 Data 25
71 DQ26 DQ26 DQ26 Data 26
72 DQ27 DQ27 DQ27 Data 27
73 VDD VDD VDD +5 VDC or +3.3 VDC
74 DQ28 DQ28 DQ28 Data 28
75 DQ29 DQ29 DQ29 Data 29
76 DQ30 DQ30 DQ30 Data 30
77 DQ31 DQ31 DQ31 Data 31
78 VSS VSS VSS Ground
79 CK2 CK2 CK2 Clock signal 2
80 n/c n/c n/c Not connected
81 n/c(WP) n/c n/c (Serial WP)
82 SDA SDA SDA Serial Data
83 SCL SCL SCL Serial Clock
84 VDD VDD VDD +5 VDC or +3.3 VDC

ピン種別定義意味
Non-P 72 ECC 80 ECC
127 VSS VSS VSS Ground
128 CKE0 CKE0 CKE0 Clock Enable Signal 0
129 /S3 /S3 /S3 Chip Select 3
130 DQMB6 DQMB6 DQMB6 Byte Mask signal 6
131 DQMB7 DQMB7 DQMB7 Byte Mask signal 7
132 A13 A13 A13 Address 13
133 VDD VDD VDD +5 VDC or +3.3 VDC
134 n/c n/c CB14 Parity/Check Bit Input/Output 14
135 n/c n/c CB15 Parity/Check Bit Input/Output 15
136 n/c CB6 CB6 Parity/Check Bit Input/Output 6
137 n/c CB7 CB7 Parity/Check Bit Input/Output 7
138 VSS VSS VSS Ground
139 DQ48 DQ48 DQ48 Data 48
140 DQ49 DQ49 DQ49 Data 49
141 DQ50 DQ50 DQ50 Data 50
142 DQ51 DQ51 DQ51 Data 51
143 VDD VDD VDD +5 VDC or +3.3 VDC
144 DQ52 DQ52 DQ52 Data 52
145 n/c n/c n/c Not connected
146 Vref,NC Vref,NC Vref,NC �
147 n/c n/c n/c Not connected
148 VSS VSS VSS Ground
149 DQ53 DQ53 DQ53 Data 53
150 DQ54 DQ54 DQ54 Data 54
151 DQ55 DQ55 DQ55 Data 55
152 VSS VSS VSS Ground
153 DQ56 DQ56 DQ56 Data 56
154 DQ57 DQ57 DQ57 Data 57
155 DQ58 DQ58 DQ58 Data 58
156 DQ59 DQ59 DQ59 Data 59
157 VDD VDD VDD +5 VDC or +3.3 VDC
158 DQ60 DQ60 DQ60 Data 60
159 DQ61 DQ61 DQ61 Data 61
160 DQ62 DQ62 DQ62 Data 62
161 DQ63 DQ63 DQ63 Data 63
162 VSS VSS VSS Ground
163 CK3 CK3 CK3 Clock signal 3
164 n/c n/c n/c Not connected
165 SA0 SA0 SA0 Serial address 0
166 SA1 SA1 SA1 Serial address 1
167 SA2 SA2 SA2 Serial address 2
168 VDD VDD VDD +5 VDC or +3.3 VDC

SPD Serial WPは内部Pull-down.

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200pin DIMM

ピン種別定義意味
193 SDA Serial Data
195 SCL Serial Clock
194 SA0 Serial address 0
196 SA1 Serial address 1
198 SA2 Serial address 2

SPD Serial WPはGND接続.

ピン	Non-P	Parity	ピン	Non-P	Parity
1	VSS	2	DQ0
3	DQ16	4	DQ1
5	DQ17	6	DQ2
7	DQ18	8	DQ3
9	DQ19	10	VCC
11	PD5	12	A0
13	A1	14	A2
15	A3	16	A4
17	A5	18	A6
19	A10	20	DQ4
21	DQ20	22	DQ5
23	DQ21	24	DQ6
25	DQ22	26	DQ7
27	DQ23	28	A7
29	A11	30	VCC
31	A8	32	A9
33	/RAS3	34	/RAS2
35	n/c	PQ3	36	n/c	PQ1
37	n/c	PQ2	38	n/c	PQ4
39	VSS	40	/CAS0
41	/CAS2	42	/CAS3
43	/CAS1	44	/RAS0
45	/RAS1	46
47	/WE	48	(/ECC)
49	DQ8	50	DQ24
51	DQ9	52	DQ25
53	DQ10	54	DQ26
55	DQ11	56	DQ27
57	DQ12	58	DQ28
59	VCC	60	DQ29
61	DQ13	62	DQ30
63	DQ14	64	DQ31
65	DQ16	66	PD2
67	PD1		PD2
69	PD3		PD4
71		72	VSS

ピン	Non-P	Parity	ピン	Non-P	Parity
1	VSS	2	DQ0
3	DQ16	4	DQ1
5	DQ17	6	DQ2
7	DQ18	8	DQ3
9	DQ19	10	VCC
11	PD1	12	A0
13	A1	14	A2
15	A3	16	A4
17	A5	18	A6
19	A10	20	DQ4
21	DQ20	22	DQ5
23	DQ21	24	DQ6
25	DQ22	26	DQ7
27	DQ23	28	A7
29	A11	30	VCC
31	A8	32	A9
33	/RAS3	34	/RAS2
35	n/c	PQ3	36	n/c	PQ1
37	n/c	PQ2	38	n/c	PQ4
39	VSS	40	/CAS0
41	/CAS2	42	/CAS3
43	/CAS1	44	/RAS0
45	/RAS1	46
47	/WE	48	(/ECC)
49	DQ8	50	DQ24
51	DQ9	52	DQ25
53	DQ10	54	DQ26
55	DQ11	56	DQ27
57	DQ12	58	DQ28
59	VCC	60	DQ29
61	DQ13	62	DQ30
63	DQ14	64	DQ31
65	DQ16	66	PD2
67	PD3	68	PD4
69	PD5	70	PD6
71	PD7	72	VSS

ピン	種別定義	意味
193	SDA	Serial Data
195	SCL	Serial Clock
194	SA0	Serial address 0
196	SA1	Serial address 1
198	SA2	Serial address 2

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3-wire シリアルEEPROM

93C46 etc. DIP/SOP 8P

CS 1 ○ 8 Vcc
SK 2 7 DC
DI 3 6 ORG
DO 4 5 GND

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I2C シリアルEEPROM

24L02 etc. DIP/SOP/SSOP/MSOP 8P

A3 1 ○ 8 Vcc
A1 2 7 #WP
A0 3 6 SCL
GND 4 5 SDA

SPD 34L02も同じ
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DIP32pin FLASH/EPROM

nc/A18 1 ○ 32 Vdd
A16 2 31 #WE
A15 3 30 A17
A12 4 29 A14
A7 5 28 A13
A6 6 27 A8
A5 7 26 A9
A4 8 25 A11
A3 9 24 #OE
A2 10 23 A10
A1 11 22 #CE
A0 12 21 DQ7
DQ0 13 20 DQ6
DQ1 14 19 DQ5
DQ2 15 18 DQ4
GND 16 17 DQ3

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DIP28pin EPROM

A15/Vpp 1 ○ 28 Vdd
A12 2 27 A14/#PGM
A7 3 26 A13
A6 4 25 A8
A5 5 24 A9
A4 6 23 A11
A3 7 22 #OE
A2 8 21 A10
A1 9 20 #CE
A0 10 19 DQ7
DQ0 11 18 DQ6
DQ1 12 17 DQ5
DQ2 13 16 DQ4
GND 14 15 DQ3
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CS	1	○	8	Vcc
SK	2	7	DC
DI	3	6	ORG
DO	4	5	GND

A3	1	○	8	Vcc
A1	2	7	#WP
A0	3	6	SCL
GND	4	5	SDA

nc/A18	1	○	32	Vdd
A16	2	31	#WE
A15	3	30	A17
A12	4	29	A14
A7	5	28	A13
A6	6	27	A8
A5	7	26	A9
A4	8	25	A11
A3	9	24	#OE
A2	10	23	A10
A1	11	22	#CE
A0	12	21	DQ7
DQ0	13	20	DQ6
DQ1	14	19	DQ5
DQ2	15	18	DQ4
GND	16	17	DQ3

A15/Vpp	1	○	28	Vdd
A12	2	27	A14/#PGM
A7	3	26	A13
A6	4	25	A8
A5	5	24	A9
A4	6	23	A11
A3	7	22	#OE
A2	8	21	A10
A1	9	20	#CE
A0	10	19	DQ7
DQ0	11	18	DQ6
DQ1	12	17	DQ5
DQ2	13	16	DQ4
GND	14	15	DQ3

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