| BYTE | 256M | 128M | 128M
THSHIBA | 64M | 64M
08K3409
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| 0 [00h] | Number of Bytes used by Module Manufacturer (General) | 128 bytes used
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| 1 [01h] | Total SPD Memory Size (General) | 256 bytes
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| 2 [02h] | Memory Type (General) | SDRAM
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| 3 [03h] | Number of Row Address Bits (SDRAM specific) | 12 row address bits
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| 4 [04h] | Number of Column Address Bits (SDRAM specific) | 10 column address bits | 9 column address bits | 8 column address bits
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| 5 [05h] | Number of Module Rows | 2 rows
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| 6-7 [06-07h] | Module Data Width | x64
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| 8 [08h] | Module Interface Signal Levels | LVTTL
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| 9 [09h] | SDRAM Cycle time (highest CAS latency) | Tclk = 10.0ns/CL3
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| 10 [0Ah] | SDRAM Access time from Clock (highest CAS latency) | Tac = 6.0ns/CL3
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| 11 [0Bh] | Module Configuration Type | Non-Parity, Non-ECC
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| 12 [0Ch] | Refresh Rate/Type | 15.625us/Self Refresh
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| 13 [0Dh] | SDRAM Width | x8 | x16 | x16 | x16 | x16
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| (Primary SDRAM) | (No Bank2 -OR- Bank2 uses same width Primary SDRAM as Bank1)
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| 14 [0Eh] | Error Checking SDRAM Width | None
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| 15 [0Fh] | SDRAM Device Attributes, Min Clock Delay for Back to Back Random Column Addresses | Tccd = 1 clock
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| 16 [10h] | SDRAM Device Attributes, Burst Lengths Supported | Burst length = 1, 2, 4, 8, Page, Supported
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| 17 [11h] | SDRAM Device Attributes, Number of Banks on SDRAM Device | 4 banks
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| 18 [12h] | SDRAM Device Attributes, CAS Latency | CAS Latency = 3, 2, Supported | CAS Latency = 3, Supported
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| 19 [13h] | SDRAM Device Attributes, CS Latency | CS Latency = 0, Supported
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| 20 [14h] | SDRAM Device Attributes, WE Latency | WE Latency = 0, Supported
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| 21 [15h] | SDRAM Module Attributes | Unbuffered
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| 22 [16h] | SDRAM Device Attributes, General
| | Early RAS# Precharge |
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| Auto-Precharge, Precharge All
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| Write 1/Read Burst
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| Supported Lower Vcc tolerance = 10%, Upper Vcc tolerance = 10%
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| 23 [17h] | SDRAM Cycle time (2nd highest CAS latency) | Tclk = 12.0ns/CL2 | Tclk = 10.0ns/CL2 | Tclk = 15.0ns/CL2 | N/A
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| 24 [18h] | SDRAM Access from Clock (2nd highest CAS latency) | Tac = 7.0ns/CL2 | Tac = 6.0ns/CL2 | Tac = 9.0ns/CL2 |
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| 25 [19h] | SDRAM Cycle time (3rd highest CAS latency) | N/A
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| 26 [1Ah] | SDRAM Access from Clock (3rd highest CAS latency) | N/A
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| 27 [1Bh] | Minimum Row Precharge Time | Trp = 20ns
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| 28 [1Ch] | Row Active to Row Active Min | Trrd = 20ns
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| 29 [1Dh] | RAS to CAS Delay Min | Trcd = 20ns
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| 30 [1Eh] | Minimum RAS Pulse Width | Tras = 50ns
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| 31 [1Fh] | Density of Each Row on Module | Row = 128MB | Row = 64MB | Row = 32MB
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| 32 [20h] | Command and Address signal input setup time | 2.0ns
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| 33 [21h] | Command and Address signal input hold time | 1.0ns
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| 34 [22h] | Data signal input setup time | 2.0ns
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| 35 [23h] | Data signal input hold time | 1.0ns
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| 62 [3Eh] | SPD Data Revision Code | Rev.1.2
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| 63 [3Fh] | Checksum for Bytes 0-62(The low 8-bits of the arithmetic sum of bytes 0)
| The checksum = 47h
(through 62. = 0547h)
| The checksum = 0Fh
(through 62. = 050Fh)
| The checksum = 0Eh
(through 62. = 050Eh)
| The checksum = 85h
(through 62. = 0585h)
| The checksum = 03h
(through 62. = 0403h)
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| 64-71 [40-47h] | Manufacturer's JEDEC ID Code
| Company Name = Samsung,
Bank = 1,
Number = 78 (DEC),
CODE = CE00000000000000 (HEX)
| None
| Company Name = Unknown,
FFFFFFFFFFFFFFFF (HEX),
" " (ASCII)
| Company Name = Hitachi,
Bank = 1,
Number = 7 (DEC),
CODE = 0700000000000000 (HEX)
| None
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| 72 [48h] | Manufacturing Location | 01h | 00h | FFh | 4Ah | 00h
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| 73-90 [49-5Ah] | Manufacturer's Part Number | M4 64S3323CN0-L1L | | | HB52D88DC-B6F |
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| 91-92 [5B-5Ch] | Revision Code | 30h, 43h | N/A | FFh, FFh | 30h, 20h | N/A
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| 93-94 [5D-5Eh] | Manufacturing Date | Year : 36, Week : 1 | Year : 0, Week : 0 | Year : 3, Week : 18 | Year : 0, Week : 34 | Year : 0, Week : 0
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| 95-98 [5F-62h] | Assembly Serial Number
| S/N : 23EE8C02 (HEX)
| S/N : 00000000 (HEX)
| S/N : FFFFFFFF (HEX)
| S/N : 5303E72E (HEX)
| S/N : 00000000 (HEX)
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| 99-125 [63-7Dh] | Manufacturer Specific Data | FF57374131303043FFFF...FF (HEX) | 0000...00 (HEX) | FFFF...FF00 (HEX) | FFFF...FF (HEX) | 0000...00 (HEX)
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| 126 [7Eh] | Intel specification for frequency | 100MHz
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| 127 [7Fh] | Intel Specification details for 100MHz Support
| CLK0 CLK1 (2clock)Connected,
Junction Temp : 100C,
CL3 Supported,
Intel defined Concurrent Auto-precharge Supported
| CLK0 CLK1 CLK2 CLK3 (4clock)Connected,
Junction Temp : 90C,
CL2 Supported,
| CLK0 CLK1 (2clock)Connected,
Junction Temp : 100C,
CL3 Supported,
Intel defined Concurrent Auto-precharge Supported
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